To address the scaling requirements of today's electronic devices, chip designers and manufacturers are constantly trying to devise circuit designs that best maximize available chip space. The resulting designs often extend to several different planes. For example, one such three-dimensional circuit design might involve a number of different device layers oriented in a stacked configuration.
When constructing a circuit in a stacked configuration it is a common practice to attach the device layers to one another using oxide-to-oxide bonding. For example, if there are two device layers involved, a handle wafer (commonly a glass wafer) is typically attached to one of the device layers and used to carry that device layer for oxide-to-oxide bonding with the other device layer. There are, however, drawbacks associated with this type of conventional three-dimensional fabrication process.
In the conventional process, each device layer is generally formed from a thin silicon-on-insulator (SOI) wafer on a substrate. The insulator, in this case an oxide, provides the basis for the oxide-to-oxide bond. Specifically, as described above, the handle wafer is attached to one of the device layers. The substrate is then removed from that device layer to expose the insulator (oxide), so as to permit the oxide-to-oxide bonding with the other device layer. Removal of the substrate is generally done by grinding or selective etching. These removal processes, however, can damage the exposed insulator (oxide). Any resulting surface unevenness and/or irregularities can negatively affect the quality of the subsequent oxide-to-oxide bond with the other device layer.
As such, there exists a need for improved three-dimensional integrated circuit integration techniques.